Summary

The course studies techniques to exploit Instruction-Level Parallelism (ILP) statically and dynamically. It also addresses some aspects of the design of domain-specific accelerators. Finally, it explores security challenges based on microarchitectural features and hardware isolation techniques.

Content

Keywords

Processors, Instruction Level Parallelism, Systems-on-Chip, Embedded Systems, High-Level Synthesis, Hardware Security.

Learning Prerequisites

Required courses

• CS-208 Architecture des ordinateurs or Computer Architecture I

Recommended courses

• CS-209 Architecture des systèmes-on-chip or Computer Architecture II

Important concepts to start the course

Undergraduate knowledge of digital circuit design and of computer architecture

Learning Outcomes

By the end of the course, the student must be able to:

• Design strategies to exploit instruction level parallelism in processors.
• Contrast static and dynamic techniques for instruction level parallelism.
• Design effective processor (micro-)architectures for which efficient compilers can be written.
• Develop hardware accelerators competitive to best commercial processors
• Defend against security threats based on microarchitectural processor features

Teaching methods

Courses, labs, and compulsory homeworks.

Assessment methods

Labs, homeworks, and final exam.

Supervision

Resources

Virtual desktop infrastructure (VDI)

No

Bibliography

• John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufman, 6th edition, 2017.

Ressources en bibliothèque

• Computer Architecture / Hennessy

Moodle Link

• https://moodle.epfl.ch/course/view.php?id=15017

Prerequisite for

• CS-471 Advanced Multiprocessor Architecture