Lab in advanced VLSI design

EE-490(b) / 4 credits

Teacher(s): Burg Andreas Peter, Levisse Alexandre Sébastien Julien

Language: English

Withdrawal: It is not allowed to withdraw from this subject after the registration deadline.

Summary

this class covers advanced VLSI design techniques. top-down full custom circuit design.

Content

Schematic edition. Advanced simulation techniques for CMOS circuits. Complex parametric analysis and multiparametric optimization. Floorplanning. Clock distribution network. Physical design and layout. Optimization for parasitics mitigation. Post layout analysis and optimization. defend their design choices in a presentation.

Keywords

VLSI

circuit design

CMOS

 

Learning Prerequisites

Recommended courses

Fundamentals of VLSI, EE-429

 

Important concepts to start the course

CMOS schematic and layout edition with Cadence virtuoso

Simulation of circuits using cadence ADE

 

Learning Outcomes

By the end of the course, the student must be able to:

  • Justify their choices
  • Optimize a circuit
  • Plan their time properly
  • Implement their plan
  • Explore various possibilities
  • Assemble a complex design
  • Estimate the remaining effort
  • Decide what to do

Transversal skills

  • Plan and carry out activities in a way which makes optimal use of available time and other resources.
  • Continue to work through difficulties or initial failure to find optimal solutions.
  • Make an oral presentation.

Teaching methods

lecture

guided labs

project

Expected student activities

attendance at lectures

doing a project

preparing an oral presentation

Supervision

Office hours Yes
Assistants Yes
Forum Yes

Resources

Virtual desktop infrastructure (VDI)

Yes

Moodle Link

In the programs

  • Semester: Spring
  • Exam form: During the semester (summer session)
  • Subject examined: Lab in advanced VLSI design
  • TP: 4 Hour(s) per week x 14 weeks
  • Type: optional
  • Semester: Spring
  • Exam form: During the semester (summer session)
  • Subject examined: Lab in advanced VLSI design
  • TP: 4 Hour(s) per week x 14 weeks
  • Type: optional
  • Semester: Spring
  • Exam form: During the semester (summer session)
  • Subject examined: Lab in advanced VLSI design
  • TP: 4 Hour(s) per week x 14 weeks
  • Type: optional

Reference week

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