EE-334 / 4 credits

Teacher: Burg Andreas Peter

Language: English


Summary

Students will acquire basic knowledge about methodologies and tools for the design, optimization, and verification of custom digital systems/hardware. They learn how to design synchronous digital circuits on register transfer level, analyse their timing and implement them in VHDL and on FPGAs.

Content

Keywords

Digital hardware component/system, register-transfer-level design, RTL, VHDL, synthesis, verification, FPGA.

Learning Prerequisites

Required courses

Logic systems (CS-171). Microcontrollers and digital systems design (EE-208).

Important concepts to start the course

Combinational and sequential logic components. Basic computing unit architecture.

Learning Outcomes

By the end of the course, the student must be able to:

  • Explain the principles and rules for safe and robust synchronous design.
  • Optimize datapaths for timing and area.
  • Develop state machines and control structures for digital circuits.
  • Translate a register-transfer-level design into a synthesizable VHDL model.
  • Synthesize datapaths and control from a high-level specification to FPGA.
  • Test the correct functionality of RTL and synthesized VHDL models.

Teaching methods

Ex-cathedra with exercises in groups and small projects using FPGA design tools and platforms.

Expected student activities

Attending lectures. Completing exercises and projects. Use FPGA design tools.

Assessment methods

 Graded Homework and Final Exam

Resources

Bibliography

R. Airiau, et al., VHDL: Langage, modélisation, synthèse, Presses Polytechniques et Universitaires Romandes, 2003.

H. Kaeslin, Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge Univ. Press, 2008.

A. Rushton, VHDL for Logic Synthesis, 3rd ed.: Wiley, 2011.

Ressources en bibliothèque

Notes/Handbook

Lecture handouts and notes. VHDL syntax summary. FPGA design tools user's guides.

Prerequisite for

TL in Micro and nanoelectronics, TP in micro-nano, EDA-Based Design, Fundamentals of VLSI

In the programs

  • Semester: Fall
  • Exam form: During the semester (winter session)
  • Subject examined: Digital systems design
  • Lecture: 2 Hour(s) per week x 14 weeks
  • Exercises: 2 Hour(s) per week x 14 weeks
  • Semester: Fall
  • Exam form: During the semester (winter session)
  • Subject examined: Digital systems design
  • Lecture: 2 Hour(s) per week x 14 weeks
  • Exercises: 2 Hour(s) per week x 14 weeks
  • Semester: Fall
  • Exam form: During the semester (winter session)
  • Subject examined: Digital systems design
  • Lecture: 2 Hour(s) per week x 14 weeks
  • Exercises: 2 Hour(s) per week x 14 weeks

Reference week

 MoTuWeThFr
8-9  GCC330
CO6
CO260
  
9-10    
10-11  GCC330
CO020
CO260
  
11-12    
12-13     
13-14     
14-15     
15-16     
16-17     
17-18     
18-19     
19-20     
20-21     
21-22     

Wednesday, 8h - 10h: Lecture GCC330
CO6
CO260

Wednesday, 10h - 12h: Exercise, TP GCC330
CO020
CO260