Fiches de cours 2017-2018

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Hardware systems modeling

EE-434

Enseignant(s) :

Vachoux Alain

Langue:

English

Summary

This course addresses the main aspects of the modeling of digital and mixed-signal hardware components and systems using the VHDL and the VHDL-AMS modeling languages.

Content

Introduction

System-on-chip (SoC) design issues. Design methodologies and design tasks. Notion of model. Modeling formalisms for digital and mixed-signal systems. Simulation and synthesis techniques.

Modeling digital hardware components and systems

Essential VHDL language elements and modeling concepts. VHDL synthesis subset. Modeling combinational and sequential/synchronous behaviors. Register-transfer level (RTL) modeling: modeling control (finite-state machines - FSM), modeling datapath, pipelining, generic RTL architecture (FSMD, algorithmic state machine (ASM)). From algorithm to digital hardware.

Modeling analog and mixed-signal hardware components and systems

Essential VHDL-AMS language elements and modeling concepts. Modeling electrical primitives, operational amplifier, filters, A/D and D/A interfaces, A/D and D/A converters.

Keywords

Digital hardware modeling. Analog and mixed-signal hardware modeling. VHDL. VHDL-AMS.

Learning Prerequisites

Required courses

Circuits and systems. Logic systems. Integrated digital circuits design. Analog circuits design.

Important concepts to start the course

Circuit and systems theory. Combinational and sequential logic components. Analog functional blocks (operational amplifier, filter, etc.).

Learning Outcomes

By the end of the course, the student must be able to:

Teaching methods

Lectures with integrated exercises.

Expected student activities

Attending lectures. Completing exercises. Using state-of-the-art electronic design automation (EDA) tools.

Assessment methods

Homework exercises (20%). Final examination including a quiz and problems (80%).

Supervision

Office hours No
Assistants Yes
Forum Yes

Resources

Bibliography

P. Ashenden, G. Peterson, and D. Teegarden, The System Designer's Guide to VHDL-AMS, Morgan Kaufmann, 2002.

J. Bergeron, et al., Verification Methodology Manual for SystemVerilog, Springer, 2005.

P.P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-Interscience, 2006.

F. Pêcheux, C. Lallement, and A. Vachoux, "VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, pp. 204-225, 2005.

A. Rushton, VHDL for Logic Synthesis, 3rd ed.: Wiley, 2011.

Ressources en bibliothèque
Notes/Handbook

Course notes. VHDL and VHDL-AMS documentation. EDA tools user's guide.

Websites
Moodle Link

Dans les plans d'études

Semaine de référence

 LuMaMeJeVe
8-9     
9-10     
10-11     
11-12 DIA005   
12-13    
13-14     
14-15     
15-16     
16-17     
17-18     
18-19     
19-20     
20-21     
21-22     
 
      Cours
      Exercice, TP
      Projet, autre

légende

  • Semestre d'automne
  • Session d'hiver
  • Semestre de printemps
  • Session d'été
  • Cours en français
  • Cours en anglais
  • Cours en allemand